Cloud native EDA tools & pre-optimized hardware platforms
Synopsys® VC Verification IP for JEDEC DDR5 provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DDR5/4/3/2 based designs.
This VIP is based on next generation architecture and implemented in native SystemVerilog/UVM. It is natively integrated with Verdi® Protocol and Memory Analyzer for easy and fast debug and Verdi Performance Analyzer to find and fix performance bottlenecks.
The availability of Synopsys' design-proven DDR5 VIP delivers a new level of confidence to end customers by enabling verification closure of industry-first JEDEC 1.0 DDR5 devices."
Malcolm Humphrey
|Vice President of Marketing, Micron
Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.