VC Verification IP for GDDR6

Memory Model Certification

Synopsys provides a comprehensive set of DRAM and Flash Memory VIP that support the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI. Synopsys’ VIP team works closely with leading memory vendors to certify 100% compatibility with their manufactured parts. Synopsys Memory VIP is used by memory controller and PHY IP design teams for verification sign off using run time and random JEDEC, and vendor part selection, protocol, and timing checks, and functional coverage. The early adoption and collaboration with leading memory vendors, SoC market makers, and industry leading IP teams certify the quality of Synopsys Memory VIP.

Highlights

• Native SystemVerilog/UVM
• Access to vendor specifications
• Runs natively on major simulators
• Runtime JEDEC and vendor part selection 
• Verification plan and coverage
• Built-in protocol and timing checks
• Verdi Protocol and Memory Analyzer
• Built-in performance analysis metrics
• Dynamic reconfiguration
• Backdoor memory/mode registers access
• Bypass/fast initialization
• Trace file and debug ports for easy debug

Key Features

• GDDR specification JESD205C
• 16 bank and bank group modes
• DDR and QDR data rate support
• Memory densities (4Gb to 16Gb per channel)
• All data rates (16Gbps/pin, 14Gbps/pin, 12Gbps/pin)
• All commands
• All mode registers
• GDDR6 trainings
• RDQS and DQ preamble
• EDC half and full rate support
• CRC half and full rate support
• WRITE Data mask function
• Data bus inversion (DBI) & Command Address bus inversion (CABI)
• x8/x16 mode configuration
• Pseudo-channel mode (PC mode) configuration 
• Support PRBS