Cloud native EDA tools & pre-optimized hardware platforms
Synopsys IC Validator™ physical verification high-performance signoff solution improves productivity for customers at all process nodes, from mature to advanced. Synopsys IC Validator offers the industry’s best distributed processing scalability to over 4,000 CPU cores. The tool’s performance and scalability enabled some of the industry’s largest reticle limit chips with billions of transistors, same-day design rule checking (DRC), layout versus schematic (LVS), and fill turnaround time.
IC Validator is seamlessly integrated with the Synopsys Fusion Compiler™ RTL-to-GDSII solution and IC Compiler® II place and route system in the Synopsys Digital Design Family. This integrated fusion technology accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment.
Nvidia’s Senior Manager for Hardware Engineering, Ramulu Undevalli shares how he and his team used Synopsys IC Validator™ for physical verification and achieved significant time savings.
Intel’s Senior SoC Design Engineer, Matt Nichelson talks about the physical verification challenges his team faced and how Synopsys IC Validator™ helped to meet those challenges with significant results.
Learn how IC Validator PERC enables designers to do a broad set of complex reliability verification checks at cell level, block level and full chip level.