Cloud native EDA tools & pre-optimized hardware platforms
Synopsys' comprehensive high-speed SerDes IP portfolio with leading power, performance, and area, allows designers to meet the efficient connectivity requirements of high-performance computing SoCs for hyperscale data center, networking, and storage applications.
224G Ethernet PHY IP and 112G Ethernet PHY IP enable true long reach channels as part of the industry's first Complete 1.6T Ethernet IP Solution
56G Ethernet PHY IP addresses reach and performance of up to 400G Ethernet applications
Die-to-Die PHY IP for UCIe and 112G XSR
Multi-Protocol PHYs supports Ethernet, PCI Express, CCIX, CXL and more protocols
PCI Express PHY IP enables high-performance, power-efficient connectivity for up to 64GT/s SoCs on advanced FinFET processes
800G Ethernet Subsystem Link-Level Interop Success with Ecosystem at ECOC 2023
DSP Techniques For High-Speed SerDes
800G Ethernet Subsystem Linkup, FEC Stats and Performance Demo
Synopsys 224G Ethernet PHY IP at TSMC Symposium
Synopsys and OpenLight Electro-Optical Link Demo
Synopsys 224G, 112G Ethernet PHY IP and PCIe 6.0 IP at DesignCon 2023
Synopsys 224G and 112G Ethernet PHY IP Demonstrations at OIF & OFC 2023
Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability
100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers
The Controller Designers Need for 1.6 Terabits per Second Ethernet Interfaces
Latency Considerations For 1.6T Ethernet Designs
Key MAC Considerations for the Road to 1.6T Ethernet Success
How Are the Standards for the Terabit Era Defined?
800Gs Finally Breaking out and Benefits of Solution
The Impact of UCIe on Multi-Die Systems
Application Challenges to get to 1.6T using 224G Ethernet
How an ASIC Model for IP Can Accelerate Semiconductor Innovation
The Role of Synopsys High-Speed SerDes for Future Ethernet Applications